An integrated circuit packaged device generally includes an integrated circuit chip lying on a chip support pad. Wire bonds connect the IC to a lead frame. A substance, such as plastic, encapsulates the structure. The plastic small outline J lead (PSOJ) package is one exemplary example. For application, one technique uses reflow solder to surface mount the IC package to a printed circuit board.
As the industry moves towards thinner packages and packages containing chips of larger size for higher volumetric packaging, new packaging techniques are evolving. One such technique is the lead over chip package, (LOC). As described in the article entitled Volume Production of Unique Plastic Surface Mount Modules For The IBM 80-ns 1-Mbit DRAM Chip by Area Wire Bond Techniques by William C. Ward, published at the 38th ECC in IEEE 1988, pages 552-557, this technique disposes a lead frame over the active area of an integrated circuit. Adhesive insulating tape attaches the lead frame to the integrated circuit chip. Wire bonds connect the circuit to the centrally disposed power supply busses. And, wire bonds jump over the power supply busses to connect the integrated circuit to conductive lead fingers. No chip support pad is required.
Concerns exist about potential wire bond shorting to the power bus portions of the lead frame in the LOC package. Since the wires to the signal pins cross the metal lead frame power bus, the opportunity for shorting may arise from assembly processes such as poor bond location, wire loop control, mold compound sweep, or from accidental touching during processing.
One approach to minimize shorting problems suggests the use insulated wire. See, Insulated Aluminum Bonding Wire For High Lead Count Packaging by Alex J. Oto, International Journal For Hybrid Microelectronics, Vol. 9, No. 1, 1986. While insulated wire has been reported to have some degree of success in conventional assembly packages, the successful implementation in a LOC package is questionable due to the nature of the wire bond stitch as it occurs over the insulating film on top of the integrated circuit; the probability of successful implementation is therefore less likely. Additionally, insulated wire is expensive.
Concerns also exist about potential delamination between the molding compound used to encapsulate the package and the metallic lead frame in the LOC package. Delamination in the vicinity of the wire bonds can cause shear failures resulting in breakage of the wire bonds.
Additionally, with respect to both conventionally packaged devices and LOC packaged devices, delamination of mold compound creates a significant problem resulting in plastic package cracking during attachment to a printed circuit board. During reflow solder, the heat generated by the process can enhance the state of thermal mismatch between dissimilar materials in the IC package creating high stresses. During the reflow solder process, where the temperature ranges between about 215 C. to 260 C., any moisture that may be present in the encapsulating mold compound is converted to steam. The steam pressure can cause delamination and package cracking. In order to avoid this problem, "dry packing" is typically required.
It is an object of this invention to provide a solution to wire bond shorting in lead over chip integrated circuit packaged devices.
It is a further object of this invention to provide a solution to package cracking in both lead over chip integrated circuit packaged devices and conventionally packaged devices.
Other objects and benefits of this invention will be apparent to those of ordinary skill in the art having the benefit of the description to follow herein.